DRAFT: Flexible interconnection network for dynamically reconfigurable architectures

Author

Devaux, Ludovic ; Ben Sassi, Sana ; Pillement, Sebastien ; Chillet, Daniel ; Demigny, Didier

Author_Institution

IRISA, Univ. of Rennes 1, Lannion, France

fYear

2009

fDate

9-11 Dec. 2009

Firstpage

435

Lastpage

438

Abstract

Dynamic and partial reconfiguration allows to place on line the various tasks that describe an application, in available regions of an FPGA. This new feature leads notably to communication problems since tasks are not present in the matrix during all computation time. In this article, we compare popular interconnection architectures. From this study, the DRAFT network is designed to support the communication constraints required by the dynamic reconfiguration. DRAGOON, the automatic generator of networks providing the DRAFT topology, is presented with DRAFT first implementation results and network performances.

Keywords

field programmable gate arrays; multiprocessor interconnection networks; reconfigurable architectures; DRAFT network; DRAGOON; FPGA; automatic networks generator; dynamic reconfiguration adapted fat-tree; dynamically reconfigurable architectures; flexible interconnection network; Bandwidth; Computer architecture; Delay; Field programmable gate arrays; Hardware; Job shop scheduling; Multiprocessor interconnection networks; Network topology; Network-on-a-chip; Reconfigurable architectures;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2009. FPT 2009. International Conference on

Conference_Location

Sydney, NSW

Print_ISBN

978-1-4244-4375-8

Electronic_ISBN

978-1-4244-4377-2

Type

conf

DOI

10.1109/FPT.2009.5377642

Filename

5377642