Efficient implementation of fast redundant number adders for long word-lengths in FPGAs

The use of redundant number systems can significantly improve computational performance in numerically intensive applications, however, the implementation of their arithmetic circuits is usually expensive because multiple bits are needed for each symbol (digit). This paper presents efficient adder circuits specifically targeted to the low cost FPGA architectures of the Xilinx Spartan 3 and the Altera Cyclone III. The special carry logic and fast carry chains are re-purposed to serve the new adders. These circuits use the redundancy in representation to eliminate carry propagation, providing near constant addition delay irrespective of the operand width. This is confirmed experimentally and shown to outperform the architecture optimised binary ripple carry adders. The critical path delay cross over for the binary and binary signed digit adders are at widths of 44 and 24 symbols, using only 2 and 3 times the number of look-up tables on the Spartan 3 and Cyclone III respectively. Fast prefix-tree adders do not compare favourably at any width.