Performance analysis of circuit-switched traffic over a packet network

The performance of circuit-switched traffic over packet networks is analyzed. It is shown that the analytical model for the N-port queue gives a good estimate for sizing buffers at these queues. It is also shown that, by scheduling packets to prevent them from arriving back-to-back at the output queue, the buffer requirements at the output queue as well as the variance in the queuing delays can be reduced considerably. Finally, by mixing higher-speed continuous streams with several low-speed continuous streams with several low-speed continuous streams, variability in the low-speed stream´s arrival process can be reduced. This fact can be used to advantage at call setup time. By operating the system at a lower utilization (<100%), and by proper choice of traffic mix, the number of buffers required to achieve a given packet blocking probability as well as the delay and the variance in the queuing delays can be minimized