Modified structures for power-efficient level translators

Reducing the supply voltage of a digital integrated circuit decreases the power consumption and also the circuit speed. One effective way for low-power design of digital integrated circuits is to employ two or multiple supply voltages in a way that smaller voltages are employed for slower circuits and larger voltages for faster blocks. This, however, necessitates the use of interface blocks called level converters or level translators. In this paper, two modified structures are proposed for low-power implementation of level converters. Simulation results of the circuits in a 0.18-μm CMOS technology confirm the power efficiency of the proposed circuits.