Efficient multiprocessor architecture for digital signal processing

There is a continuing pressure of better processing performances in numerical signal processing. Effective utilization of LSI semiconductor technology allows the consideration of multiprocessor architectures. The problem of interconnecting the components of the architecture arises. In this paper we describe a control algorithm of the Benes interconnection network in a asynchronous multiprocessor system. A simulation study of the timeshared bus, of the omega network, of the Benes network and of the crossbar network gives a comparison of performances.