A scalable memory interface for multicore reconfigurable computing systems

Embedded multicore devices require high performance with minimal power consumption; many systems use dedicated hardware units to meet these constraints. However, embedded systems have also become increasingly multi-purpose and must be able to execute a wide range of applications - some of which might not yet be known at design time. It is therefore difficult to choose an appropriate mix of dedicated hardware that meets a device´s size, cost, and capability constraints. A reconfigurable hardware coprocessor is a potential solution, as it is highly effective at accelerating a variety of different tasks (which need not necessarily be known in advance), and does so using less energy than general purpose processors. In this work, we first describe a method for sharing a single reconfigurable fabric amongst multiple processors on the same chip. We then examine the scalability of the memory subsystem that joins these resources, and determine methods to improve its performance to maximize acceleration. In this work, we show that our RH coprocessor model allows multiple applications to share a single RH fabric. Furthermore, we show that application performance does not significantly degrade as we increase the number of cores sharing a single coprocessor.