Pipelined parallel test structure for mixed-signal SoCs

Testing of mixed-signal SoCs becomes one of the pressing challenges due to enormous test cost including ATE expenses, design for test (DFT) hardware overhead and test application time. Prior researches focus mainly on minimizing test cost for digital SoCs under the constraint of ATE test resources and power consumption. A self-hold analog test wrapper design and pipelined parallel test manner are proposed in this paper to realize both core-level and system-level parallel test for low to mid-frequency analog cores in mixed-signal SoCs.