DocumentCode
3053471
Title
Test power reduction in compression-based reconfigurable scan architectures
Author
Almukhaizim, Sobeeh ; Mohammad, Mohammad Gh ; Khajah, Mohammad
Author_Institution
Comput. Eng. Dept., Kuwait Univ., Safat, Kuwait
fYear
2010
fDate
24-28 May 2010
Firstpage
249
Lastpage
249
Abstract
We present a method for test power reduction in compression-based reconfigurable scan architectures. In addition to their key objective of minimizing Test Data Volume (TDV), we illustrate how the distribution of care bits in scan chains can be manipulated with the objective of reducing the number of transitions during test. Hence, peak and average power of shift and capture operations are effectively reduced.
Keywords
reconfigurable architectures; testing; care bits; compression-based reconfigurable scan architectures; scan chains; test data volume; test power reduction; Circuit testing; Computer architecture; Constraint optimization; Cost function; Encoding; Power engineering and energy; Power engineering computing; Statistical analysis; System testing; Systems engineering and theory;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location
Praha
ISSN
1530-1877
Print_ISBN
978-1-4244-5834-9
Electronic_ISBN
1530-1877
Type
conf
DOI
10.1109/ETSYM.2010.5512742
Filename
5512742
Link To Document