Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints

In this preliminary study, we evaluate a reconfigurable low-power duplication-based Concurrent Error Detection (CED) infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit, resulting in the retention of the input values to the duplicate circuit (i.e., reduction in power dissipation) at the cost of some reduction in CED coverage. The results indicate that power dissipation is commensurate with CED coverage, motivating the use of LFSR structures to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.