DocumentCode
3053593
Title
Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization
Author
Gören, Sezer ; Ugurdag, H. Fatih ; Palaz, Okan
Author_Institution
Dept. of Comput. Eng., Bahcesehir Univ., Istanbul, Turkey
fYear
2010
fDate
24-28 May 2010
Firstpage
246
Lastpage
246
Abstract
This paper addresses the NP-complete problem of mapping a logic function on to a nanocrossbar with a known defect map. We first show that this problem can be transformed into a Bipartite SubGraph Isomorphism (BSGI) problem. Then we present our proposed KNS-2DS algorithm, which canonizes both graphs in N2 time (N being the number of nodes) and then matches them in N3 time in the worst case. KNS-2DS uses a K-Neighbor Sort (KNS) to initialize our main contribution 2D-Sort (2DS). 2DS is an iterative rough canonizer that lets a straightforward matching algorithm complete the job. Our algorithm offers very short run-times (due to canonization) compared to previous work and has success on all benchmarks. KNS-2DS is also novel from the perspective of the BSGI problem in the sense that it is based on canonization but not on a search tree with backtracking.
Keywords
computational complexity; graph theory; iterative methods; logic arrays; nanoelectronics; tree searching; 2D sort; KNS-2DS algorithm; NP complete problem; bipartite subgraph isomorphism; defect aware nanocrossbar logic mapping; iterative rough canonizer; k-neighbor sort; logic function mapping; search tree; CMOS logic circuits; Diodes; Iterative algorithms; Logic functions; NP-complete problem; Nanowires; Programmable logic arrays; Reconfigurable architectures; Reconfigurable logic; Runtime; Bipartite Subgraph Isomorphism; Fault Tolerance; Nanelectronics; Reconfigurable Architectures;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location
Praha
ISSN
1530-1877
Print_ISBN
978-1-4244-5834-9
Electronic_ISBN
1530-1877
Type
conf
DOI
10.1109/ETSYM.2010.5512747
Filename
5512747
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