DocumentCode
3053633
Title
Ultra high performance insulator channel transistor
Author
Zhang, Dawei ; Ferrier, Marlene ; Griffin, Peter ; Nishi, Yoshio ; Skotnicki, Thomas
Author_Institution
Electr. Eng., Stanford Univ., Stanford, CA
fYear
2008
fDate
9-11 Sept. 2008
Firstpage
141
Lastpage
144
Abstract
In this paper, an insulator channel planar transistor with ultra-high on-current, steep sub-threshold slope and superior scalability is presented. This device concept is proven by Sen Taurus device simulator with a quantum mechanic tunneling model and by a home made model utilizing transmission matrix theory.
Keywords
insulators; matrix algebra; transistors; insulator channel planar transistor; quantum mechanic tunneling model; steep sub-threshold slope; transmission matrix theory; ultra high performance insulator; Dielectrics and electrical insulation; Microelectronics; Permittivity; Potential energy; Probability; Scalability; Shape control; Solid modeling; Tunneling; Voltage; insulator channel; on current; scalability; subthreshold slope;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on
Conference_Location
Hakone
Print_ISBN
978-1-4244-1753-7
Type
conf
DOI
10.1109/SISPAD.2008.4648257
Filename
4648257
Link To Document