• DocumentCode
    3053655
  • Title

    Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli

  • Author

    Sousa, Leonel

  • Author_Institution
    TULisbon, Lisbon
  • fYear
    2007
  • fDate
    25-27 June 2007
  • Firstpage
    240
  • Lastpage
    250
  • Abstract
    The non-positional nature of residue number systems (RNS) is very useful to achieve carry free arithmetic. However it makes the comparison of numbers more difficult than in the traditional weighted number systems: there is no any efficient general method for magnitude comparison in RNS. Moreover, magnitude comparison for RNS that rely on pairs of conjugate moduli, which are not relatively prime moduli sets recently proposed because of the large dynamic ranges and the simplicity of the arithmetic units, is a new unsolved problem. In this paper an efficient method and a VLSI architecture is proposed for magnitude comparison in RNS based on sets formed by two pairs of conjugate moduli. This proposed method is much more efficient than the other known ones and is the only one valid for moduli sets not formed by relatively prime integers. The method has been applied to design a very fast Sum-of-Absolute Differences (SAD) unit for motion estimation in video sequences that performs the function entirely within the RNS channels. Experimental results show that this new SAD unit, implemented in the internal memory blocks of the xc2vp50-7 FPGA, is capable of achieving the high throughput required to perform real-time motion estimation in high resolution images.
  • Keywords
    VLSI; field programmable gate arrays; image resolution; image sequences; motion estimation; residue number systems; video signal processing; FPGA; RNS; VLSI architecture; arithmetic units; carry free arithmetic; conjugate moduli; high resolution images; magnitude comparison; motion estimation; residue number systems; sum-of-absolute differences; video sequences; Cathode ray tubes; Computer architecture; Digital arithmetic; Dynamic range; Field programmable gate arrays; Image converters; Motion estimation; Throughput; Very large scale integration; Video sequences;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic, 2007. ARITH '07. 18th IEEE Symposium on
  • Conference_Location
    Montepellier
  • ISSN
    1063-6889
  • Print_ISBN
    0-7695-2854-6
  • Type

    conf

  • DOI
    10.1109/ARITH.2007.16
  • Filename
    4272871