An adaptive tester architecture for volume diagnosis

Volume diagnosis is crucial for discovering the root causes of yield loss during the IC production flow. This process is time consuming and requires appropriate test equipment supporting diagnostic data storage. This paper proposes a novel methodology for significantly reducing the time and the data storage requirements for digital circuit diagnosis, based on a suitable tester architecture that adapts at run-time the diagnosis process, according to a fault dictionary being a part of the diagnosis recipe. When the pattern application process reaches its end, the tester directly returns a fault hypothesis. Results obtained on the ITC99 benchmarks including full scan chains demonstrate effectiveness and efficiency of the approach. The average diagnosis time reduction achieved by using the proposed solution reaches up to 92%.