Clamp Placement Optimization in Full-Chip ESD (Electro-Static-Discharge) Design

A simulation approach is presented that allow early visibility, guidance, and analysis of clamp placement in early design stage (power template design) on a chip level complexity. The ESD robustness of product is largely attributed to the degree of correct implementation of ESD design rules in a highly complex design. Correct clamp placements is the most difficult and less guidance. Therefore, an \´intelligent\´ ESD clamp placement analysis is urgently needed. This tool aims to provide a preliminary guidance of clamp placement. It provides the information of where the most probable clamp placement is in the particular power template design. Since it takes into consideration the ESD ohm rules requirements during the construction of ohm sector, it would have a very high confident level that the design would not encounter much issue in the ESD resistance checkout later. Some TLP (transient line pulse) testing has proven this approach could deliver a promising ESD protection robustness. In short, the real strength of this tool is the ability to provide earlier design guidance & optimization options starting from the product concept phase (power template design stage), which allows to align ESD with all design issues on a cost and time efficient way. Without the tool, designer would need to manually calculate the resistance, rely on past experience and some assumption with nil data support which is tedious & error prone for complex design. This allows ESD design rules compliance in the early design stage, thus enhancing the approach of "correct-by-construction" on ESD design.