Advanced annealing strategies for the 32 nm node

Author

Kampen, C. ; Martinez-Limia, A. ; Pichler, P. ; Burenkov, A. ; Lorenz, J. ; Ryssel, H.

Author_Institution

Fraunhofer Inst. of Integrated Syst. & Device Technol., Erlangen

fYear

2008

fDate

9-11 Sept. 2008

Firstpage

317

Lastpage

320

Abstract

In this work, the influences of advanced annealing schemes, spike and flash annealing and combinations of them, on the electrical behavior of modern FD SOI MOSFETs have been investigated by numerical simulations. Process simulations have been performed for comparing the two-dimensional diffusion behavior of the dopants under the different annealing schemes. Device simulations have been performed for making conclusions about how the different annealing schemes are influencing the static and dynamic behavior of modern CMOS devices.

Keywords

CMOS integrated circuits; MOSFET; annealing; numerical analysis; semiconductor process modelling; silicon-on-insulator; 2D diffusion behavior; CMOS devices; FD SOI MOSFET; electrical behavior; flash annealing; numerical simulations; process simulations; spike annealing; Boron; Doping; Electron devices; Epitaxial growth; MOS devices; MOSFETs; Predictive models; Silicon on insulator technology; Simulated annealing; Temperature distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on

Conference_Location

Hakone

Print_ISBN

978-1-4244-1753-7

Type

conf

DOI

10.1109/SISPAD.2008.4648301

Filename

4648301