Synthetic soft error rate simulation considering neutron-induced single event transient from transistor to LSI-chip level

Author

Hane, Masami ; Nakamura, Hideyuki ; Tanaka, Katsuhiko ; Watanabe, Kentaro ; Tosaka, Yoshiharu ; Ishikawa, Kiyoshi ; Kumashiro, Shigetaka

Author_Institution

MIRAI-SELETE, Sagamihara

fYear

2008

fDate

9-11 Sept. 2008

Firstpage

365

Lastpage

368

Abstract

Soft error phenomena induced by the Sea-level cosmic neutron have been investigated by using a simulation system that covers from an individual MOSFET device level to an LSI-chip level. This system consists of the several kinds of simulation codes/tools, such as a mixed-mode 3D device simulator, SPICE circuit simulator, and analyzing tools of gate-level net-lists. A comprehensive practical simulation flow is demonstrated in this paper on commercial 90 nm generation logic devices and standard-cells.

Keywords

MOSFET; circuit simulation; cosmic ray neutrons; large scale integration; LSI-chip level; MOSFET device; SPICE circuit simulator; logic devices; mixed-mode 3D device simulator; neutron-induced single event transient; sea-level cosmic neutron; soft error phenomena; synthetic soft error rate simulation; Analytical models; Circuit simulation; Circuit testing; Databases; Discrete event simulation; Error analysis; MOSFET circuits; Pulse circuits; SPICE; Space vector pulse width modulation; Single Event Transient; Soft Error; simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on

Conference_Location

Hakone

Print_ISBN

978-1-4244-1753-7

Type

conf

DOI

10.1109/SISPAD.2008.4648313

Filename

4648313