A two-dimensional transistor placement for cell synthesis

Proposes a transistor placement algorithm to generate standard cell layout in a 2D placement style that is not restricted to row-based transistor placement. The cost function constructed for transistor placement optimization is able to optimize wirings directly and diffusion sharing indirectly but sufficiently. This transistor placement algorithm, applied to several standard cells, has demonstrated the capability to generate a nearly-optimal 2D placement that is comparable to manually designed placement