Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform

Growing bandwidth of network connections as well as strong progress in network protocols and new applications require efficient and flexible network hardware. Network processors are applied for packet processing in routers and gateways. Unfortunately, deep-packet processing tasks lack the support of dedicated co-processors. Because of numerous time-consuming algorithms required, a dynamically re- configurable co-processor for network processors backing payload processing was proposed. It performs computationally intensive tasks without loss of flexibility. A crucial issue is the interconnect of such a system. Bus-based interconnects are explored utilising a software model of this co-processor to determine the performance impact of the on-chip interconnection on the overall performance of the co-processor. A single bus as well as a multiple bus system are evaluated. With regard to reconfiguration overhead, the simulation results show strength and weakness of both systems by latency, throughput, and packet buffer requirements.