Effects of fin width on memory windows in FinFET ZRAMs

Author

Zhang, E.X. ; Fleetwood, D.M. ; Mamouni, F.E. ; Alles, M.L. ; Schrimpf, R.D. ; Xiong, W. ; Cristoloveanu, S.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA

fYear

2009

fDate

9-11 Dec. 2009

Firstpage

1

Lastpage

2

Abstract

In this paper, the effects of fin width on transient coupling for nMOS and pMOS FinFET transistors was evaluated as a function of applied back gate bias during the write pulse, and the gate length dependence of impact-ionization effects was also evaluated for potential ZRAM operation on SOI substrate. It was observed that the scaling trends with decreasing fin width were unfavorable for the backgate pulse technique, but highly favorable for impact ionization. The results obtained for highly scaled FinFETs programmed via impact ionization are quite promising for potential future technology insertion.

Keywords

DRAM chips; MOSFET; impact ionisation; silicon-on-insulator; FinFET ZRAMs; SOI substrate; Si; applied back gate bias; backgate pulse technique; fin width effects; gate length dependence; impact-ionization effects; memory windows; nMOS FinFET transistor; pMOS FinFET transistor; write pulse; zero-capacitor DRAMs; Current measurement; Electrons; FinFETs; Impact ionization; MOS devices; MOSFETs; Pulse measurements; Silicon on insulator technology; Space vector pulse width modulation; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2009. ISDRS '09. International

Conference_Location

College Park, MD

Print_ISBN

978-1-4244-6030-4

Electronic_ISBN

978-1-4244-6031-1

Type

conf

DOI

10.1109/ISDRS.2009.5378208

Filename

5378208