Multi-bit sigma-delta TDC architecture with self-calibration

Author

Uemori, S. ; Ishii, M. ; Kobayashi, Hideo ; Doi, Yoshihito ; Kobayashi, Osamu ; Matsuura, T. ; Niitsu, Kiichi ; Arakawa, Yasuhiko ; Hirabayashi, Daiki ; Yano, Yuichiro ; Gake, T. ; Takai, N. ; Yamaguchi, Takahiro J.

Author_Institution

Dept. of Electron. Eng., Gunma Univ., Kiryu, Japan

fYear

2012

fDate

2-5 Dec. 2012

Firstpage

671

Lastpage

674

Abstract

This paper describes the architecture and principles of operation of sigma-delta (ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications; they offer good accuracy with short test times. In particular, we describe a multi-bit ΣΔ TDC architecture for fast testing. However, mismatches among delay cells in delay lines degrade the linearity there. Then we propose a self-calibration method that measures delay values using an improved ring oscillator circuit to improve the overall TDC linearity. Our MATLAB simulation results demonstrate the effectiveness of the proposed approach.

Keywords

calibration; sigma-delta modulation; time-digital conversion; ΣΔ time-to-digital converters; MATLAB simulation; delay cells; delay lines; high-speed I/O interface circuit test applications; multibit sigma-delta TDC architecture; ring oscillator circuit; selfcalibration method; Clocks; Delay; Frequency measurement; Ring oscillators; Sigma delta modulation; Multi-bit; Self-Calibration; Sigma-Delta Modulation; Time Measurement; Time-to-Digital Converter;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1728-4

Type

conf

DOI

10.1109/APCCAS.2012.6419124

Filename

6419124