Investigation on the clamping voltage self-balancing of the three-level capacitor clamping inverter

Author

Yuan, Xiaoming ; Stemmler, Herbert ; Barbi, Ivo

Author_Institution

Power Electron. & Electrometrol. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland

Volume

2

fYear

1999

fDate

1999

Firstpage

1059

Abstract

This paper deals with the self-balancing quality of the clamping voltage in the three-level capacitor clamping inverter due to the spontaneous clamping capacitor current control loop in the circuit. Self-balancing quality of the three-level capacitor clamping inverter under sub-harmonic PWM modulation is analyzed in detail. The self-balancing mechanism in the multilevel capacitor clamping inverter (M>3) under sub-harmonic PWM modulation is also discussed. Test results regarding the self-balancing quality from a half-bridge three-level capacitor clamping inverter prototype under sub-harmonic PWM modulation is given

Keywords

PWM power convertors; bridge circuits; electric current control; clamping voltage self-balancing; half-bridge three-level capacitor clamping inverter; multilevel capacitor clamping inverter; self-balancing quality; spontaneous clamping capacitor current control loop; sub-harmonic PWM modulation; three-level capacitor clamping inverter; Capacitors; Clamps; Diodes; Laboratories; Leg; Power electronics; Pulse width modulation inverters; Switches; Voltage control; Zero voltage switching;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics Specialists Conference, 1999. PESC 99. 30th Annual IEEE

Conference_Location

Charleston, SC

ISSN

0275-9306

Print_ISBN

0-7803-5421-4

Type

conf

DOI

10.1109/PESC.1999.785642

Filename

785642