A System Exploration Platform for Network-on-Chip

Network-on-Chip (NoC) is a key component in the design of many cores on a chip. This paper presents a new system level NoC simulation framework, called “Network-On-Chip-centric System Exploration Platform” (NOCSEP). It divides NoC design space into blocks and models them using abstracted layers. Together with task-graph software modeling and simplified middle-layer modeling, it can estimate the performance of an on-chip interconnect rapidly and is therefore very suitable for quickly exploring design alternatives.