Design of an ASIP processor for MD5 hash algorithm

ASIP (Application Specific Instruction set Processor) makes compromise between ASIC (Application Specific Integrated Circuit) and DSP (Digital Signal Processing) processor in terms of speed, cost, and flexibility parameters. Considering these unique properties of ASIP processors, design of an ASIP-based processor for MD5 (Message-Digest 5) hash algorithm is presented in this paper for the first time. Three structures named RCO (Register Configuration 0), RC1, and RC2 have been proposed. The third design has the minimum number of clock pulses in order to execute specific instructions. Proposed design has been simulated with VHDL code in the behavioral level of abstraction.