• DocumentCode
    3062548
  • Title

    A Test Model for Hardware and Software

  • Author

    Sziray, József

  • Author_Institution
    Dept. of Inf., Szechenyi Univ., Gyor, Hungary
  • fYear
    2011
  • fDate
    12-14 Dec. 2011
  • Firstpage
    292
  • Lastpage
    293
  • Abstract
    The paper presents a unified test model which is a mapping scheme for describing the one-to-one correspondence between the input and output domains of a given hardware or software system. Here the test inputs and the fault classes are also involved. The test model incorporates both the verification and the validation schemes for the hardware and software.
  • Keywords
    program testing; program verification; fault classes; hardware-software test model; mapping scheme; validation schemes; verification schemes; Computational modeling; Computers; Fault detection; Hardware; Software systems; Testing; Hardware testing; software testing; verification and validation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Dependable Computing (PRDC), 2011 IEEE 17th Pacific Rim International Symposium on
  • Conference_Location
    Pasadena, CA
  • Print_ISBN
    978-1-4577-2005-5
  • Electronic_ISBN
    978-0-7695-4590-5
  • Type

    conf

  • DOI
    10.1109/PRDC.2011.41
  • Filename
    6133099
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3062548