Design of a high speed 12-bit subranging A/D converter

Author

Ruoxu, Wang

Author_Institution

Sichuan Inst. of Solid State Circuits, Chongqing, China

fYear

1998

fDate

1998

Firstpage

389

Lastpage

392

Abstract

A high-speed 12-bit subranging analog-to-digital converter (ADC) is presented in the paper. Adapted in the circuit is a 3-stage subranging architecture of “3-bit+3-bit+8-bit”, in which the 8-bit ADC is a folding and interpolating ADC, and the error correction is accomplished by analog correction and digital encoding. For fabrication techniques, the 2 μm design rule, polysilicon-gate BiCMOS process, laser trimmed SiCr thin film resistor network and double metal routing are employed. SPICE simulation shows a 3 MHz sampling rate has been achieved at ±5 V power supply

Keywords

BiCMOS integrated circuits; SPICE; analogue-digital conversion; high-speed integrated circuits; integrated circuit design; 12 bit; 2 micron; 3 MHz; 5 V; SPICE simulation; analog correction; circuit architecture; circuit design; digital encoding; double metal routing; error correction; folding ADC; high-speed subranging analog-to-digital converter; interpolating ADC; laser trimmed SiCr thin film resistor network; polysilicon gate BiCMOS process; Analog-digital conversion; BiCMOS integrated circuits; Encoding; Error correction; Optical design; Optical device fabrication; Resistors; Routing; SPICE; Thin film circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-4306-9

Type

conf

DOI

10.1109/ICSICT.1998.785903

Filename

785903