FPGA implementation of RSA cryptoalgorithm using shift and carry algorithm

One of possible ways of RSA cryptoalgorithm with a very long key implementation, besides most commonly used Montgomery´s algorithm, is shift and carry algorithm. In this paper FPGA implementation of this algorithm is presented, where a key is 1024 bits long. Appropriate VHDL model for RSA was written. Project synthesis results (resource occupancy and maximal operating frequency), as well as results of software and hardware testing are shown. Brief comparison of this project with implementations based on Montgomery´s algorithm is stated at the end.