InP-based HEMTs for high speed, low power circuit applications

Author

Adesida, I. ; Mahajan, A. ; Cueva, G.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1998

fDate

1998

Firstpage

579

Lastpage

582

Abstract

Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 μm gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, g_mext, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of-over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated

Keywords

HEMT integrated circuits; III-V semiconductors; direct coupled FET logic; field effect logic circuits; high electron mobility transistors; high-speed integrated circuits; indium compounds; low-power electronics; prescalers; 0.3 micron; 95 GHz; InP; InP HEMT; buried Pt gate; cut-off frequency; depletion-mode HEMT; direct coupled FET logic; enhancement-mode HEMT; high-speed low-power circuit; monolithic integration; prescaler; threshold voltage; transconductance; Cutoff frequency; D-HEMTs; FETs; HEMTs; Indium phosphide; Lattices; MODFETs; Monolithic integrated circuits; Threshold voltage; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-4306-9

Type

conf

DOI

10.1109/ICSICT.1998.785953

Filename

785953