DocumentCode
3066891
Title
High-speed VLSI implementation of reduced complexity sequence estimation algorithms with application to Gigabit Ethernet 1000Base-T
Author
Haratsch, Erich F.
Author_Institution
Lucent Technol., AT&T Bell Labs., Holmdel, NJ, USA
fYear
1999
fDate
1999
Firstpage
171
Lastpage
174
Abstract
This paper compares reduced complexity sequence estimation (RCSE) algorithms in terms of SNR performance, VLSI implementation, hardware complexity and critical path. A novel architecture is presented which reduces the hardware complexity of RCSE and relaxes the critical path problem. This architecture can be used to implement RCSE for Gigabit Ethernet 1000Base-T
Keywords
VLSI; decision feedback equalisers; high-speed integrated circuits; local area networks; trellis coded modulation; twisted pair cables; Gigabit Ethernet 1000Base-T; RCSE; SNR performance; VLSI implementation; critical path; hardware complexity; high-speed VLSI implementation; reduced complexity sequence estimation algorithms; Crosstalk; Decision feedback equalizers; Ethernet networks; Hardware; Intersymbol interference; Maximum likelihood decoding; Maximum likelihood estimation; Resource management; USA Councils; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-5620-9
Type
conf
DOI
10.1109/VTSA.1999.786027
Filename
786027
Link To Document