Design challenges for high-performance SOI digital CMOS VLSI

Author

Chuang, C.T.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1999

fDate

1999

Firstpage

270

Lastpage

273

Abstract

This paper reviews the recent advances of SOI for high-performance digital CMOS VLSI applications. The technology/device requirements and design issues/challenges for high-performance, general-purpose microprocessor applications are differentiated with respect to low-power portable applications. Particular emphasis is placed on the impact of floating-body in partially-depleted devices on the circuit operation, stability, and functionality. Unique SOI design aspects such as the parasitic bipolar effect and hysteretic V_T variation are addressed. Circuit techniques to improve the noise immunity and global design issues are discussed

Keywords

CMOS digital integrated circuits; VLSI; circuit stability; integrated circuit design; integrated circuit noise; low-power electronics; microprocessor chips; silicon-on-insulator; SOI design aspects; circuit operation; circuit techniques; design challenges; floating-body; functionality; general-purpose microprocessor applications; global design issues; high-performance SOI digital CMOS VLSI; hysteretic threshold voltage variation; low-power portable applications; noise immunity; parasitic bipolar effect; partially-depleted devices; stability; technology/device requirements; CMOS process; CMOS technology; Circuit noise; Circuit stability; Hysteresis; Immune system; Microprocessors; Process design; Silicon on insulator technology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.786052

Filename

786052