A testable design to test pattern sensitive faults efficiently for semiconductor RAM

The authors present a testable design to test pattern sensitive faults efficiently for semiconductor random access memories to reduce test time and hence test cost. Testability was achieved by including additional hardware. The additional hardware is composed of a special mode counter, an error checker, a modified column decoder, and one extra control pinout. The functional test procedure proposed is of length 512 (1+n^1/2) read and write operations for an n cell memory, and covers stuck-at, transition, coupling, and nine-cell neighborhood pattern sensitive faults. This design has an estimated overhead of 5% chip area and one additional pinout