Access paths and testing in an ultra high-performance ATM switch

Author

Butner, steven E.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

fYear

1998

fDate

16-18 Feb 1998

Firstpage

373

Lastpage

378

Abstract

This paper discusses the architecture and testing of an ultra high performance 4-input, 4-output asynchronous transfer mode (ATM) switch that has been designed as part of the DARPA-sponsored “Thunder and Lightning” project at the University of California, Santa Barbara. This research project is focused on the design and prototype demonstration of ATM links and switches operating at or above 40 gigabits per second per link (TDM), with potential scalability to 100 Gbit/sec. Such aggressive link rates place severe requirements on switch architecture, particularly the buffering scheme. We discuss the access paths and test techniques used in the development and verification of this electronic ATM switch and describe reasons for the main design choices

Keywords

asynchronous transfer mode; buffer storage; electronic equipment testing; electronic switching systems; time division multiplexing; 100 Gbit/s; 40 Gbit/s; ATM links; DARPA; Santa Barbara; Thunder and Lightning project; University of California; access paths; asynchronous transfer mode; buffering; electronic ATM switch; link rates; prototype demonstration; research project; switch architecture; switch design; test techniques; Asynchronous transfer mode; Bandwidth; Circuit testing; Computer architecture; Laboratories; Packet switching; Prototypes; Routing; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Performance, Computing and Communications, 1998. IPCCC '98., IEEE International

Conference_Location

Tempe/Phoenix, AZ

ISSN

1097-2641

Print_ISBN

0-7803-4468-5

Type

conf

DOI

10.1109/PCCC.1998.660071

Filename

660071