DocumentCode
3069436
Title
A 1 Gb/s, 4-state, sliding block Viterbi decoder
Author
Black, P.J. ; Meng, T.H.-Y.
Author_Institution
Inf. Syst. Lab., Stanford Univ., CA, USA
fYear
1993
fDate
19-21 May 1993
Firstpage
73
Lastpage
74
Abstract
In recent years there has been great interest in the implementation of high-speed Viterbi decoders. A potential application which has pushed decode rates into the Gb/s range is convolutional coding for optical channels. In this paper, an alternative sliding block Viterbi decoder is proposed that approaches ideal linear scaling (complexity proportional to speedup) without constraining the encoding process. Sliding block Viterbi decoder implementation of the Viterbi algorithm as a sliding block decoder (SBD) is based on the observation that the state at time n can be decoded using only the information from the interval n-L to n +L, where L is the survivor path length.
Keywords
CMOS integrated circuits; block codes; codecs; decoding; maximum likelihood estimation; 4-state sliding block Viterbi decoder; CMOS technology; Gb/s range; Viterbi algorithm; complexity proportional; convolutional coding; decode rates; encoding process; high-speed Viterbi decoders; ideal linear scaling; optical channels; pushed decode; survivor path length; CMOS integrated circuits; Codecs; Sliding-block coding; Viterbi decoding;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location
Kyoto, Japan
Type
conf
DOI
10.1109/VLSIC.1993.920543
Filename
920543
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