A single-chip CMOS transceiver for DCS-1800 wireless communications

This CMOS transceiver chip for the DCS-1800 wireless communication system is realized in a 0.25 /spl mu/m CMOS process. The realization of a CMOS transceiver that complies with the specifications of a high-quality digital-wireless system requires overall integration of architecture, building block and transistor-level design. A highly-integrated architecture minimizes the number of high-frequency external nodes, as these are difficult to drive with CMOS circuits. Up- and downconversion topologies allow at the same time mixing and a high-quality on-chip single-ended to differential conversion. Extra buffers between building blocks optimize overall circuit performance.