Processing TSV wafer with stealth dicing technology

Conventional wafer dicing technology used on one side RDL structure of normal wafer is performed by blade dicing. Nowadays, it applies to through silicon via (TSV) wafer with double side RDL structure which emerges to serve a wide range of 3DIC applications that demands higher levels of performance and heterogeneity integration. However, the phenomenon of severe back-side chipping (BSC) occurs on the bottom surface of the wafer because of its exclusive structure. BSC may cause yield loss when micro-cracks exceeds the seal ring and also results in circuit damage and reliability failure of package device. To develop a method of chipping-free dicing, currently, stealth dicing (SD) is the best way for chip separation and its another distinguished advantage over other dicing methods is the completed dry process. Nevertheless, because of the limitation due to laser dynamic focal point, the warpage of ultra thin wafer is a critical challenge for SD. In this paper, SD technology used on TSV wafer was proposed, for the purpose of resolving warpage issue and reducing BSC, two dicing methods were applied to this study. Following by the study, chipping-free dicing is accomplished and a smooth surface is obtained, and the study method that the flat modified layer is formed with better performance in warpage.