DocumentCode
3074923
Title
Performance evaluation of adaptivity in software transactional memory
Author
Payer, Mathias ; Gross, Thomas R.
Author_Institution
ETH Zurich, Zurich, Switzerland
fYear
2011
fDate
10-12 April 2011
Firstpage
165
Lastpage
174
Abstract
Transactional memory (TM) is an attractive platform for parallel programs, and several software transactional memory (STM) designs have been presented. We explore and analyze several optimization opportunities to adapt STM parameters to a running program. This paper uses adaptSTM, a flexible STM library with a non-adaptive baseline common to current fast STM libraries to evaluate different performance options. The baseline is extended by an online evaluation system that enables the measurement of key runtime parameters like read- and write-locations, or commit- and abort-rate. The performance data is used by a thread-local adaptation system to tune the STM configuration. The system adapts different important parameters like write-set hash-size, hash-function, and write strategy based on runtime statistics on a per-thread basis. We discuss different self-adapting parameters, especially their performance implications and the resulting trade-offs. Measurements show that local per-thread adaptation outperforms global system-wide adaptation. We position local adaptivity as an extension to existing systems. Using the STAMP benchmarks, we compare adaptSTM to two other STM libraries, TL2 and tinySTM. Comparing adaptSTM and the adaptation system to TL2 results in an average speedup of 43% for 8 threads and 137% for 16 threads. adaptSTM offers performance that is competitive with tinySTM for low-contention benchmarks; for high-contention benchmarks adaptSTM outperforms tinySTM. Thread-local adaptation alone increases performance on average by 4.3% for 16 threads, and up to 10% for individual benchmarks, compared to adaptSTM without active adaptation.
Keywords
concurrency control; multi-threading; software performance evaluation; transaction processing; STAMP benchmarks; STM library; daptSTM; hash-function; performance evaluation; software transactional memory; thread-local adaptation system; write strategy; write-set hash-size; Adaptive systems; Benchmark testing; Bioinformatics; Libraries; Optimization; Runtime; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance Analysis of Systems and Software (ISPASS), 2011 IEEE International Symposium on
Conference_Location
Austin, TX
Print_ISBN
978-1-61284-367-4
Electronic_ISBN
978-1-61284-368-1
Type
conf
DOI
10.1109/ISPASS.2011.5762733
Filename
5762733
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