Real time discrete cosine transform an original architecture

This paper presents an original hardware architecture for a two-dimensional real time Discrete Cosine Transform (DCT) processor for television signals. The work has been focused on low power consumption, low cost and minimum size because of the necessity (at least for the expander) to insert the equipment in the subscriber´s home. The basic element of the transformer consists of a single chip 2D-DCT processor working on (8 × 8) blocks of 8 bits with an objective cycle time of 100 ns. The highly pipelined structure of the processor is optimized for the Fast Discrete Cosine Transform (FDCT) algorithm proposed by W.H. Chen and al [1]. In order to satisfy speed and resolution constraints for real time compression of television signals, four of these basic DCT processors need to work in parallel, controlled by two Direct Memory Access Controllers (DMAC). This architecture compares favourably with other works published in the literature [2] [3].