DocumentCode
3079049
Title
Diagnosing scan chain timing faults through statistical feature analysis of scan images
Author
Chen, Mingjing ; Orailoglu, Alex
Author_Institution
CSE Dept., UC San Diego, La Jolla, CA, USA
fYear
2011
fDate
14-18 March 2011
Firstpage
1
Lastpage
6
Abstract
Excessive test mode power-ground noise in nanometer scale chips causes large delay uncertainties in scan chains, resulting in a highly elevated rate of timing failures. The hybrid timing violation types in scan chains, plus their possibly intermittent manifestations, invalidate the traditional assumptions in scan chain fault behavior, significantly increasing the ambiguity and difficulty in diagnosis. In this paper, we propose a novel methodology to resolve the challenge of diagnosing multiple permanent or intermittent timing faults in scan chains. Instead of relying on fault simulation that is incapable of approximating the intermittent fault manifestation, the proposed technique characterizes the impact of timing faults by analyzing the phase movement of scan patterns. Extracting fault-sensitive statistical features of phase movement information provides strong signals for the precise identification of fault locations and types. The manifestation probability of each fault is furthermore computed through a mathematical transformation framework which accurately models the behavior of multiple faults as a Markov chain. The fault model utilized in the proposed scheme considers the effect of possibly asymmetric fault manifestation, thus maximally approximating the realistic failure behavior. Simulations on large benchmark circuits and two industrial designs have confirmed that the proposed methodology can yield highly accurate diagnosis results even for complicated fault manifestations such as multiple intermittent faults with mixed fault types.
Keywords
Markov processes; design for testability; fault diagnosis; feature extraction; nanoelectronics; probability; statistical analysis; timing; Markov chain; asymmetric fault manifestation; benchmark circuit; design for testability; fault-sensitive statistical feature extraction; hybrid timing violation type; industrial design; intermittent timing fault diagnosis; manifestation probability; mathematical transformation framework; nanometer scale chip; permanent timing fault diagnosis; phase movement analysis; scan chain timing fault diagnosis; statistical feature analysis; test mode power-ground noise; timing failure; Circuit faults; Correlation; Fault location; Image segmentation; Mathematical model; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location
Grenoble
ISSN
1530-1591
Print_ISBN
978-1-61284-208-0
Type
conf
DOI
10.1109/DATE.2011.5763040
Filename
5763040
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