An all-digital built-in self-test technique for transfer function characterization of RF PLLs

This paper presents an all-digital built-in self-test (BIST) technique for characterizing the error transfer function of RF PLLs. This BIST scheme, with on-chip stimulus synthesis and response analysis completely done in the digital domain, achieves high-accuracy characterization and is applicable to a wide range of PLL architectures. For the popular sigma-delta fractional-N RF PLLs, the added circuitry required for this BIST solution is all digital except a bang-bang phase-frequency detector (BB-PFD), which incurs an area of only 0.0001 mm² for our implementation in a 65 nm CMOS technology. The silicon characterization results at 3.6 GHz reported by this BIST solution and by explicit measurement have a root-mean-square difference of 0.375 dB only.