Developing a high speed beamformer using the TMS320C6201 digital signal processor

We are developing a synthetic aperture beamformer for a realtime 3D imaging system. The beamformer consists of a network of multi-processor digital signal processor (DSP) boards which provide the processing speed and flexibility required for realtime 3D beamforming. The system uses high speed memory buffers and a ribbon cable interface between DSP boards to allow channel to channel transfers to occur in parallel. Each channel has a 12 bit A/D, a C6201 DSP which calculates delayed signal values using linear interpolation, and a DSP for summing. Dividing the summing and delaying tasks reduces the input/output (I/O) burden. Restricting the A/D sampling frequency to an integer multiple of four times the center frequency of the ultrasound signal further reduces the I/O burden. An algorithm optimized for the C6201 calculates a single demodulated point in 25 ns. A multi-resolution look up table algorithm produces an 8 bit estimate of the log compressed envelope signal in less than 25 ns per point. Simulations of the radiation pattern formed using three transmit pulses show secondary lobes below -50 dB