Large scale input and output buffered ATM switch

Author

Yoshikawa, Suminori ; Nagano, Hiroshi ; Suzuki, Toshio ; Nakane, Hideki ; Shinohara, Masayulu ; Murase, Tutomu ; Ramamurthy, Gopalakrishnan

Author_Institution

Switching Div., NEC Corp., Chiba, Japan

fYear

1999

fDate

1999

Firstpage

115

Lastpage

120

Abstract

ATM switches, which serve as nodes in ATM public backbone networks, are required to have a large capacity due to the increase of traffic. This paper proposes a large-scale ATM switch architecture providing 160 Gbit/s switching capability. It is such that the output buffered switch elements are expanded in square grids. Our switch architecture achieves non-blocking and multi-QoS guarantee. As a way to ensure multi-QoS, we employ a stop-shape-go (SSG) congestion control method and its performance is evaluated by simulation

Keywords

asynchronous transfer mode; buffer storage; multistage interconnection networks; quality of service; telecommunication congestion control; telecommunication traffic; ATM switch; buffered switch elements; capacity; large-scale switch; multi-QoS guarantee; nodes; non-blocking architecture; performance evaluation; public backbone networks; simulation; square grids; stop-shape-go congestion control; traffic; Asynchronous transfer mode; Communication switching; Communication system control; IP networks; Laboratories; Large-scale systems; National electric code; Round robin; Spine; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

ATM Workshop, 1999. IEEE Proceedings

Conference_Location

Kochi

Print_ISBN

4-88552-164-5

Type

conf

DOI

10.1109/ATM.1999.786847

Filename

786847