A 100 Mb/s CMOS 100Base-T4 Fast Ethernet transceiver for category 3, 4 and 5 UTP

Author

Chan, K. ; Berman, M. ; Kruse, D. ; Lu, F. ; Tran, H. ; Yousefi, N. ; Samueli, H.

Author_Institution

Broadcom Corp., Irvine, CA, USA

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

208

Lastpage

209

Abstract

A 100Base-T4 Fast Ethernet transceiver based on a DSP approach supports 100 Mb/s over low-grade CAT3 unshielded twisted pair (UTP) as well as higher grade CAT4 and 5 UTP. The transceiver performs all the required physical layer (PHY) interface functions from the media-independent interface (MII) to filterless magnetic module in a single CMOS chip.

Keywords

CMOS digital integrated circuits; 100 Mbit/s; 100Base-T4 Fast Ethernet transceiver; CAT3 UTP; CAT4 UTP; CAT5 UTP; CMOS chip; DSP; filterless magnetic module; media-independent interface; physical layer interface; unshielded twisted pair; Bit error rate; Clocks; Decoding; Delay; Equalizers; Ethernet networks; Intersymbol interference; Magnetic separation; Physical layer; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672438

Filename

672438

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3082096