• DocumentCode
    3082243
  • Title

    Modeling manufacturing process variation for design and test

  • Author

    Kundu, Sandip ; Sreedhar, Aswin

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Massachusetts at Amherst, Amherst, MA, USA
  • fYear
    2011
  • fDate
    14-18 March 2011
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    For process nodes 22nm and below, a multitude of new manufacturing solutions have been proposed to improve the yield of devices being manufactured. With these new solutions come an increasing number of defect mechanisms. There is a need to model and characterize these new defect mechanisms so that (i) ATPG patterns can be properly targeted, (ii) defects can be properly diagnosed and addressed at design or manufacturing level. This presentation reviews currently available defect modeling and test solutions and summarizes open issues faced by the industry today. It also explores the topic of creating special test structures to expose manufacturing process parameters which can be used as input to software defect models to predict die specific defect locations for better targeting of test.
  • Keywords
    lithography; semiconductor device manufacture; semiconductor device reliability; semiconductor device testing; ATPG patterns; defect mechanisms; defect modeling; manufacturing process variation; Layout; Lithography; Logic gates; Resists; Semiconductor device modeling; Defect Modeling; Fault Diagnosis; Layout Enhancements for Manufactuing; Manufacturing test; Photolithography;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
  • Conference_Location
    Grenoble
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-61284-208-0
  • Type

    conf

  • DOI
    10.1109/DATE.2011.5763192
  • Filename
    5763192