Low-cost advanced encryption standard (AES) VLSI architecture: a minimalist bit-serial approach

This paper presents a novel minimum cost architecture for the advanced encryption standard (AES) algorithm. This architecture uses a bit-serial approach, and it is suitable for VLSI implementations. By utilizing a true bit-serial design, this architecture can be used for cost sensitive applications that require high security, such as security system human interfaces, point of sale terminals, and infotainment kiosks. This AES architecture can be used as a coprocessor integrated with an inexpensive microcontroller in a system-on-a-chip (SoC) platform. The prototyping of the architecture is presented as well.