An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation

We present a STA tool based on a single-pass true path computation that efficiently determines the critical path list Given that it does not rely on a two-step process it can be programmed to find efficiently the N true paths from a circuit We also report and analyze the dependence of complex gates delay with the sensitization vector and its variation (that gets up to 15% in 65 nm technologies), and consider such effect in the path delay estimation Delay is computed from a simple polynomial analytical description that requires a one-time library parameter extraction process, making it highly scalable. Results on combinational ISCAS synthesized for three technologies (130 nm, 90 nm and 65 nm) provide better results in computation time, number of paths reported and delay estimation for these paths compared to a commercial tool.