Embedding test patterns into Low-Power BIST sequences

Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional built-in self test (BIST) generators rise the power and energy consumption during testing, boosting the need to add low-power solutions to the arsenal of BIST pattern generators. In this work, the utilization of gray code generators is proposed as a low-power BIST solution; more precisely, we propose an algorithm to embed a test pattern into a sequence generated by a gray code generator. Hence, test sets can be embedded into gray sequences.