A commercial multithreaded RISC processor

Author

Storino, S. ; Aipperspach, A. ; Borkenhagen, J. ; Eickemeyer, R. ; Kunkel, S. ; Levenstein, S. ; Uhlmann, G.

Author_Institution

IBM Corp., Rochester, MN, USA

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

234

Lastpage

235

Abstract

Implementation of a coarse-grained hardware-multithreaded processor for use in the IBM AS1400 uses a PowerPC architecture that supports two threads. Hardware multithreading is a technique for tolerating memory latency by utilizing otherwise idle cycles in the CPU. This requires the replication of the processor architecture registers for each thread. Replication is not required for the majority of processor logic such as instruction cache, data cache, TLB, instruction fetch and dispatch mechanisms, branch units, fixed-point units, floating-point units, and storage-control units.

Keywords

reduced instruction set computing; IBM AS1400; PowerPC architecture; RISC processor; TLB; branch units; coarse-grained hardware-multithreaded processor; data cache; dispatch mechanisms; fixed-point units; floating-point units; idle cycles; instruction cache; instruction fetch; memory latency; processor architecture registers; processor logic; storage-control units; Circuits; Delay; Ground penetrating radar; Hardware; Logic; Pipelines; Reduced instruction set computing; Registers; Switches; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672449

Filename

672449