DocumentCode
3084876
Title
Multiple-cell-upset hardened 6T SRAM using NMOS-centered layout
Author
Yoshimoto, Shusuke ; Nii, Koji ; Kawaguchi, Hitoshi ; Yoshimoto, Masahiko
Author_Institution
Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan
fYear
2013
fDate
5-6 June 2013
Firstpage
98
Lastpage
99
Abstract
This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.
Keywords
CMOS integrated circuits; CMOS memory circuits; SRAM chips; radiation hardening (electronics); 6T SRAM macro; CMOS process; MCU SER; NMOS-centered layout; hardened 6T SRAM; irradiated neutron; memory size 1 MByte; neutron-accelerated test; neutron-induced multiple-cell-upset; size 65 nm; Educational institutions; Layout; MOS devices; Neutrons; SRAM cells; Transistors; SRAM; multiple cell upset (MCU); neutron particle; soft error rate (SER); triple well; twin well;
fLanguage
English
Publisher
ieee
Conference_Titel
Future of Electron Devices, Kansai (IMFEDK), 2013 IEEE International Meeting for
Conference_Location
Suita
Print_ISBN
978-1-4673-6106-4
Type
conf
DOI
10.1109/IMFEDK.2013.6602257
Filename
6602257
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