From the present to the future: Scaling of planar VLSI-CMOS devices towards 3D-FinFETs and beyond 10nm CMOS technologies; manufacturing challenges and future technology concepts

Jan Hoentschel works for GLOBALFOUNDRIES as a Device Manager and is responsible for 28nm low power technologies. He manages an international device engineering team, which is handling several low power CMOS technologies starting from 40nm down to 28nm. Before he was working with Advanced Micro Devices and served several PD-SOI-CMOS device integrations from 130nm down to 32nm technologies for high performance microprocessors. In addition he was working within the product interaction and implementation group at AMD in Austin, TX. Jan Hoentschel is author and co-author of numerous technical papers and patents in the semiconductor field. He holds an MS and PhD in electrical engineering from the Technical University in Dresden as well as an MBA in General Management from the University of Applied Science Bielefeld. His research interests include HKMG, strain engineering, 3D FinFET device and technology concepts, lIIiV semiconductors and low power technologies on CMOS devices.