Photolithography solutions for fabrication of Fin and Poly-gate in 14nm FinFET devices

Author

Xiaobo Guo ; Xianguo Dong ; Shuxin Yao ; Zhifeng Gan ; Wuping Wang ; Zhengkai Yang ; Ermin Chong ; Quanbo Li ; Zhibiao Mao ; Liang Zhang ; Runling Li ; Yu Zhang

Author_Institution

Shanghai Huali Microelectron. Corp., Shanghai, China

fYear

2015

fDate

15-16 March 2015

Firstpage

1

Lastpage

3

Abstract

Due to good electrical characteristics and controllability, 3D-FinFET is proved to be a promising substitution of planar poly-gate devices for 20nm technology node and beyond. One of the greatest challenges is to fabricate the Fin and Poly-gate to meet device requirement. This paper describes the photolithography process as one of key solutions to form Fin and Poly-gate structure in 14nm FinFET devices. To fabricate the Fin structure, SADP (Self Aligned Double Patterning) process is introduced to obtain 25nm half pitch pattern; furthermore, the overlay performance, which is impacted by SADP process, is studied on both design of alignment/overlay mark and light source of overlay measurement. Lithography performance of LELE (Lihto-Etch-Litho-Etch) double-patterning is described in poly line formation. LEC (Line End Cutting) process with various groups of materials is discussed to improve poly line-end performance. Finally, a desired FinFET structure is successfully fabricated.

Keywords

MOSFET; nanopatterning; photolithography; FinFET devices; LEC; LELE; SADP; alignment-overlay mark; fin fabrication; fin structure; light source; lihto-etch-litho-etch; line end cutting; overlay measurement; photolithography solutions; poly line formation; poly-gate fabrication; poly-gate structure; self aligned double patterning; size 14 nm; size 20 nm; Delays; Lithography; Presses; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Technology International Conference (CSTIC), 2015 China

Conference_Location

Shanghai

ISSN

2158-2297

Type

conf

DOI

10.1109/CSTIC.2015.7153353

Filename

7153353