• DocumentCode
    3085417
  • Title

    Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction

  • Author

    Zadeh, D. Hassan ; Oomine, H. ; Kakushima, K. ; Kataoka, Yasuyuki ; Nishiyama, A. ; Sugii, Nobuyuki ; Wakabayashi, H. ; Tsutsui, K. ; Natori, K. ; Iwai, Hisato

  • Author_Institution
    Frontier Res. Center, Tokyo Inst. of Technol., Yokohama, Japan
  • fYear
    2013
  • fDate
    9-11 Dec. 2013
  • Abstract
    Ultra-thin InGaAs gate stacks with CET= 0.73 nm (EOT<; 0.5 nm), Dit as low as 8.0×1011 (cm-2 eV-1) and thermal stability up to 600°C is demonstrated by using La2O3 as gate dielectric. A silicide/InGaAs junction with excellent controllability at the interface is also proposed. These results promise the integration compatibility of this gate stack for future node 3D device structures.
  • Keywords
    III-V semiconductors; MOSFET; gallium arsenide; high-k dielectric thin films; indium compounds; lanthanum compounds; semiconductor-insulator boundaries; thermal stability; CET; In0.53Ga0.47As; La2O3; capacitance equivalent thickness; future node 3D device structure; high-k gate stack; interfacial reaction suppression; size 0.73 nm; thermally stable silicide contact; Dielectrics; Indium gallium arsenide; Junctions; Logic gates; Nickel; Thermal stability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2013 IEEE International
  • Conference_Location
    Washington, DC
  • Type

    conf

  • DOI
    10.1109/IEDM.2013.6724544
  • Filename
    6724544
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3085417